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dsPIC30F
FIGURE 9-4:
DCI MODULE BLOCK DIAGRAM
BCG Control Bits
CSCKD
F OSC /4
Word Size Selection bits
Frame Length Selection bits
DCI Mode Selection bits
Sample Rate
Generator
Frame
Synchronization
Generator
COFSD
CSCK
COFS
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
0
Transmit Buffer
Registers w/Shadow
DCI Shift Register
CSDI
CSDO
9.8
SPI TM Module
as the FSYNC, frame synchronization pulse. A device
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface for communicating with
other peripheral or microcontroller devices such as
Serial EEPROMs, shift registers, display drivers, A/D
converters, etc. It is compatible with Motorola’s SPI?
and SIOP interfaces.
This SPI module includes all SPI modes. A Frame
Synchronization mode is also included for support of
voice band codecs.
Four pins make up the serial interface: SDI, serial data
input; SDO, serial data output; SCK, shift clock input or
output; SS, active low slave select, which also serves
? 2005 Microchip Technology Inc.
set up as an SPI Master provides the serial
communication clock signal on its SCK pin.
A series of 8 or 16 clock pulses (depending on mode)
shift out the 8 or 16 bits (depending on whether a byte
or word is being transferred) and simultaneously shift
in 8 or 16 bits of data from the SDI pin. An interrupt is
generated when the transfer is complete.
Transmits and receives are double-buffered, which
allows the buffer to be used while the shift register is
still shifting data in or out. Slave Select synchronization
allows selective enabling of SPI Slave devices, which
is particularly useful when a single Master is connected
to multiple slaves.
DS70043F-page 31
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